About Me
As a Design Verification Engineer with over three years of experience, I specialize in RISC-V CPU and SoC verification. I build advanced UVM testbenches, validate hardware with C and assembly tests, and automate workflows using SystemVerilog and Python.I thrive on solving tough hardware challenges and am passionate about computer architecture. Let's connect to talk about the future of chip design and RISC-V!
Work Experience
Verification Engineer
Full Time
10xEngineers Technologies Pvt Ltd
Sep 2023 – Aug 2025
Associate Engineer
Full Time
10xEngineers Technologies Pvt Ltd
Mar – Sep 2023
Trainee Engineer
Part Time
10xEngineers Technologies Pvt Ltd
Jul 2022 – Feb 2023
Research Assistant
Internship
MEDS Lab, UET Lhr
Jan – June 2022
Teaching Assistant
Internship
UET Lhr
Jan – June 2021
Education
Bachelor of Science in Electrical and Computer Engineering
Bachelor's
University of Engineering and Technology, Lahore
Aug 2019 – Mar 2023
Intermediate in Pre-Engineering
Higher Secondary
Punjab Group of Colleges
Mar 2017 – Mar 2019
Matriculation in Science
Secondary School
Garrison Boys High School
Mar 2015 – Mar 2017
Key Achievements
Notable accomplishments and recognitions in my career
Gold Medal & High Achiever Award
Awarded the Gold Medal and prize money for outstanding performance at the LGES High Achiever Ceremony
Subject Matter Expert
Served as an SME for System Verilog verification and Intro to RISC-V Assembly & Computer Architecture courses, contributing to curriculum development and instruction at 10xE Training Department.
Level 2 Seller on Fiverr
Managed up to 170+ projects on Fiverr and Upwork delivering high-quality work within tight deadlines
170+ ProjectsComputer Architecture Instructor
Taught a Computer Architecture course to five international students from different countries through the ULAAS Academy platform.
5 International StudentsProgramming Languages
My proficiency in core verification languages
SystemVerilog
0
%
UVM
0
%
C / Python
0
%
Assembly
0
%
Technical Skills
A broader look at my capabilities in the verification domain
Functional Coverage Modeling
Constrained Random Verification (CRV)
SystemVerilog Assertions (SVA)
Testplan Creation & Traceability
Waveform Debugging & Root Cause Analysis
Regression Strategy & Management
Assertion-Based Verification (ABV)
Scoreboarding & Reference Modeling
UVM-based Testbench Architecture